Processor Model Three (PDP-3) is a high
performance, large scale digital computer featuring reliability in
operation together with economy in initial cost, maintenance and use.
This combination is achieved by the use of very fast, reliable, solid
state circuits coupled with system design restraint. The simplicity of
the system design excludes many marginal or superfluous features and
thus their attendant cost and maintenance problems.

The average internal instruction execution rate is about 100,000
operations per second with a peak rate of 200,000 operations per second.
This speed, together with its economy and reliability, recommends PDP-3
as an excellent instrument for complex real time control applications
and as the center of a modern computing facility.

PDP-3 is a stored program, general purpose digital computer. It is a
single address, single instruction machine operating in parallel on 36
bit numbers. It features multiple step indirect addressing and indexing
of addresses. The main memory makes 511 registers available as index
registers.

The main storage is coincident current magnetic core modules of 4096
words each. The computer has a built-in facility to address 8 modules
and can be expanded to drive 64 modules. The memory has a cycle time of
five microseconds.

SYSTEM BLOCK DIAGRAM

The flow of information between the various registers of PDP-3 is shown
in the System Block Diagram (Fig. 1). There are four registers of 36 bit
length. Their functions are described below.

Memory Buffer

The Memory Buffer is the central switching register. The word coming
from or going to memory is retained in this register. In arithmetic
operations it holds the addend, subtrahend, multiplicand, or divisor.
The left 6 bits of this register communicate with the Instruction
Register. The address portion of the Memory Buffer Register communicates
with the Index Adder, the Memory Address Register, and the Program
Counter. In certain instructions, the address portion of the control
word does not refer to memory but specifies variations of an
instruction, thus, the address portion of the Memory Buffer is connected
to the Control Element.

Accumulator

The Accumulator is the main register of the Arithmetic Element. Sums and
differences are formed in the Accumulator. At the completion of
multiplication it holds the high order digits of the product. In
division it initially contains the high order digits of the dividend a